1. Technical Field
The present invention relates to integrated circuitry manufacturing. In particular, the present invention relates to semiconductor packaging.
2. Description of the Related Art
Integrated circuit products include a manufactured semiconductor device or ‘chip’ mounted onto a package in order to provide electronic signal, power and ground interconnections to other devices for electronic product manufacture. This requires that the semiconductor chip be physically and electrically interconnected the packaging containing a substrate. The chip includes pads that each provide for a signal or power/ground interconnection to corresponding pads located on the substrate. Typically a solder alloy is provided on the semiconductor chip pads and on the substrate pads that are to be interconnected. Interconnection is provided during an assembly process by placing the chip pads onto the substrate pads using a high temperature to melt and reflow the solder from the semiconductor chip and the substrate to join the chip to the substrate and electrically interconnect the pads.
In some assembly processes the substrate pads include solid solder which is fabricated by applying presolder which is reflowed as part of the laminate fabrication process. When presolder is used, the reflowed solder forms domes or hemispheres due to the surface tension of the molten solder during the reflow process. FIG. 1 illustrates a chip 100 including solder bumps or domes such as 102 and 104 and a substrate 110 including solder bumps or domes 106 and 108. FIG. 2 illustrates a chip 200 including pillars 202 and 206 with solder bumps 204 and 208. In FIG. 2, the substrate 214 includes solder bumps or domes 210 and 212 similar to the substrate 110 in FIG. 1. FIG. 2 illustrates that placing the chip 200 onto the substrate 214 can result in misalignment caused by the bump or dome shapes on both the chip and semiconductor sliding laterally when during assembly resulting in a lateral shift of the chip relative to the substrate.
One prior art solution has been to flatten the bumps or domes on the substrate. This process is referred to as bump flattening or coining. However, coining adds an extra process step and requires specialized equipment. Also, coining can be a contributor to yield loss during laminate fabrication. Therefore the addition of the coining process step is expensive and can result in lower yield.
Further, as technology progresses, semiconductor chips have become more complex and chip size has decreased. This results in a greater number of smaller interconnection pads on a smaller chip surface. Therefore, alignment of the chip interconnection pads with the corresponding interconnection pads of the substrate becomes a greater challenge.